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Jobs and careers for design verification engineer from the company Data capital inc in Santa Clara (2 jobs)

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  • Data Capital Inc
  • Santa Clara
... : 3+ years of FPGA verification experience Strong SystemVerilog programming skills ... on experience with UVM (Universal Verification Methodology) Familiarity with industry- ... standard verification tools (e.g., QuestaSim, Synopsys VCS) ...
20 days ago
  • Data Capital Inc
  • Santa Clara
... : 3+ years of FPGA verification experience Strong SystemVerilog programming skills ... on experience with UVM (Universal Verification Methodology) Familiarity with industry- ... standard verification tools (e.g., QuestaSim, Synopsys VCS) ...
26 days ago