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Jobs and careers for fpga verification engineering from the company Data capital inc in Santa Clara (12 jobs)

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FPGA Verification Engineering

  • Data Capital Inc
  • Santa Clara
... : FPGA Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification experienceStrong ...
4 days ago

Lead FPGA Verification Engineer with UVM /Verilog System-Active Requirement

  • Data Capital Inc
  • Santa Clara
... FPGA Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification ... with UVM (Universal Verification Methodology) Familiarity with ... industry-standard verification tools (e.g., QuestaSim, ...
8 days ago

Lead FPGA Verification Engineer with UVM /Verilog System-Active Requirement

  • Data Capital Inc
  • Santa Clara
... : FPGA Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification experienceStrong ...
11 days ago

Lead FPGA Verification Engineer with UVM /Verilog System-Active Requirement

  • Data Capital Inc
  • Santa Clara
... FPGA Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification ... with UVM (Universal Verification Methodology) Familiarity with ... industry-standard verification tools (e.g., QuestaSim, ...
15 days ago

FPGA Verification Engineer

  • Data Capital Inc
  • Santa Clara
... coding,UVM 3+ years of FPGA verification experience Strong SystemVerilog programming ... experience with UVM (Universal Verification Methodology) Familiarity with industry ... -standard verification tools (e.g., QuestaSim, Synopsys VCS ...
24 days ago

FPGA Verification Engineer

  • Data Capital Inc
  • Santa Clara
... Description: 3+ years of FPGA verification experience Strong SystemVerilog programming ... experience with UVM (Universal Verification Methodology) Familiarity with industry ... -standard verification tools (e.g., QuestaSim, Synopsys VCS ...
16 days ago

FPGA Verification Engineer

  • Data Capital Inc
  • Santa Clara
... Description: 3+ years of FPGA verification experience Strong SystemVerilog programming ... experience with UVM (Universal Verification Methodology) Familiarity with industry ... -standard verification tools (e.g., QuestaSim, Synopsys VCS ...
19 days ago

FPGA Verification Engineer

  • Data Capital Inc
  • Santa Clara
... Description: 3+ years of FPGA verification experience Strong SystemVerilog programming ... experience with UVM (Universal Verification Methodology) Familiarity with industry ... -standard verification tools (e.g., QuestaSim, Synopsys VCS ...
22 days ago

FPGA Verification Engineer

  • Data Capital Inc
  • Santa Clara
... Description: 3+ years of FPGA verification experience Strong SystemVerilog programming ... experience with UVM (Universal Verification Methodology) Familiarity with industry ... -standard verification tools (e.g., QuestaSim, Synopsys VCS ...
23 days ago

Senior FPGA Verification Engineer

  • Data Capital Inc
  • Santa Clara
... Description: 3+ years of FPGA verification experience Strong SystemVerilog programming ... experience with UVM (Universal Verification Methodology) Familiarity with industry ... -standard verification tools (e.g., QuestaSim, Synopsys VCS ...
25 days ago

Senior FPGA Engineer

  • Data Capital Inc
  • Santa Clara
... : FPGA Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification experienceStrong ...
4 days ago

Senior FPGA Engineer

  • Data Capital Inc
  • Santa Clara
... : FPGA Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification experienceStrong ...
5 days ago
FPGA Verification Engineer Senior FPGA Engineer

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