Description: Title: RTL Design Engineer Project Location: Santa Clara, CA - ... design using Verilog HDL for implementation and debug. Read and comprehend ... synthesis and backend teams for physical implementation. EDUCATION: Bachelor's or Master's in ...
19 days ago
... : Role Title: ASIC/RTL Design Engineer - Senior Location: San Jose, CA ... portions of the design and implementation of blocks to meet functional ... requirements. Work with verification and physical design teams to achieve high ...
6 days ago