Description: Sr Verification Engineer VCS Distributed Simulation & Multi-Chip ... Verification Looking for a Senior Verification Engineer with expertise in VCS distributed ...
19 days ago
... Subsystem Looking for a Design Verification Engineer to play a key role in ... solutions. Requires strong expertise in System Verilog (SV) & UVM, with a focus ...
a day ago
... Subsystem Looking for a Design Verification Engineer to play a key role in ... solutions. Requires strong expertise in System Verilog (SV) & UVM, with a focus ...
22 days ago
... a skilled AI Scale-Out Software Engineer to build and optimize our ... expertise in deep learning, distributed systems, and low-level networking. Responsibilities ... and implement efficient distributed training systems for large-scale deep le
13 days ago