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Jobs and careers full-time for board verification engineer in Santa Clara (1 jobs)

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  • Data Capital Inc
  • Santa Clara
... Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification ... with UVM (Universal Verification Methodology)Familiarity with industry ... -standard verification tools (e.g., QuestaSim, ...
9 hours ago