Description: Job Title: RTL Engineer: Integrate RISC-V Core to ... 5+ years of experience in RTL design, SoC integration, or related ... Verilator).Deep understanding of SoC design, integration, and high-performance ... to debug and optimize designs for functiona
20 hours ago
... Title: Senior Deep Learning Engineer/AI-ML Engineer Location: Santa Clara, California ... We are team of chip design, analog and AI domain experts ...
6 hours ago