... Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification ... with UVM (Universal Verification Methodology)Familiarity with industry ... -standard verification tools (e.g., QuestaSim, ...
14 days ago
... Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification ... with UVM (Universal Verification Methodology) Familiarity with ... industry-standard verification tools (e.g., QuestaSim, ...
18 days ago
... : 3+ years of FPGA verification experience Strong SystemVerilog programming skills ... on experience with UVM (Universal Verification Methodology) Familiarity with industry- ... standard verification tools (e.g., QuestaSim, Synopsys VCS) ...
19 days ago
... : 3+ years of FPGA verification experience Strong SystemVerilog programming skills ... on experience with UVM (Universal Verification Methodology) Familiarity with industry- ... standard verification tools (e.g., QuestaSim, Synopsys VCS) ...
22 days ago
... : 3+ years of FPGA verification experience Strong SystemVerilog programming skills ... on experience with UVM (Universal Verification Methodology) Familiarity with industry- ... standard verification tools (e.g., QuestaSim, Synopsys VCS) ...
25 days ago
... : 3+ years of FPGA verification experience Strong SystemVerilog programming skills ... on experience with UVM (Universal Verification Methodology) Familiarity with industry- ... standard verification tools (e.g., QuestaSim, Synopsys VCS) ...
26 days ago
... UVM 3+ years of FPGA verification experience Strong SystemVerilog programming skills ... experience with UVM (Universal Verification Methodology) Familiarity with industry- ... standard verification tools (e.g., QuestaSim, Synopsys VCS) ...
27 days ago
... : 3+ years of FPGA verification experience Strong SystemVerilog programming skills ... on experience with UVM (Universal Verification Methodology) Familiarity with industry- ... standard verification tools (e.g., QuestaSim, Synopsys VCS) ...
28 days ago
... are seeking a Generative AI (GenAI) Design Engineer to join our team and ... such as content creation, product design, and intelligent automation.Develop forward ...
18 days ago
... Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification ... with UVM (Universal Verification Methodology)Familiarity with industry ... -standard verification tools (e.g., QuestaSim, ...
7 days ago
... Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification ... with UVM (Universal Verification Methodology)Familiarity with industry ... -standard verification tools (e.g., QuestaSim, ...
8 days ago
Description: Title: Software Engineer - Hybrid Mandatory skills: Java, Ruby, ... architecture,ASIC standard verification tools, languages, flows Description: Responsibilities: Design, build, test ...
14 days ago
... hiring a Hardware Board Failure Analysis Engineer Position type: Contract Duration: Long ... ) As a Hardware Board Failure Analysis Engineer, you will need: Must-have ... , 11 PM to 8 AM.Conduct verification of the module/ IP functionality
18 days ago
... seeking a highly skilled Hardware Design & FPGA Engineer to join our client's advanced ... in FPGA development, hardware board design, and hands-on experience working ... -edge product development. Key Responsibilities Design, implement, and validate FPGA
4 days ago
Description: Hardware Design & FPGA EngineerLocation: Santa Clara, California ... seeking a highly skilled Hardware Design & FPGA Engineer to join our client s advanced ... in FPGA development, hardware board design, and hands-on experience working ...
4 days ago
Description: Position : Generative AI (GenAI) Design Engineer (Contract) Location : Santa Clara, CA ... are seeking a Generative AI (GenAI) Design Engineer to join our team and ... such as content creation, product design, and intelligent automation. Develop ...
5 days ago
... Title: Materials Science AI Engineer Job Location: Santa Clara, ... Range: $60hr - $65hrResponsibilities: Design, develop and deploy multi-modal ... solve material physics and design problems.Aggregate, process, ... modeling and analysis.Design, develop and maintain ...
13 days ago
... looking for a AI Engineer for our client in Santa ... CA Job Title: AI Engineer Job Location: Santa Clara ... - $65hrThe Generative AI Design Engineer will design, develop, and optimize generative ... as content creation, product design, intelligent automation, and ...
15 days ago
... PythonProficient in using industry-standard design software, including Cadence Virtuoso, ... Calibre DRC, LVS toolsExperience supporting design teams working with analog and ... digital design flowsExcellent communication skills and ability ...
22 days ago
... : Job Title FPGA RTL design and Board validation Location: ... a highly skilled Senior FPGA Design Engineer with 7 to 15 years ... of experience in RTL design, IP design and development, and FPGA ... have a strong background in design debugging and a deep familiarity ...
28 days ago