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Jobs and careers for design verification engineer in Santa Clara (2 jobs)

Senior fpga verification engineer
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Senior FPGA Verification Engineer

  • Data Capital Inc
  • Santa Clara
... : 3+ years of FPGA verification experience Strong SystemVerilog programming skills ... on experience with UVM (Universal Verification Methodology) Familiarity with industry- ... standard verification tools (e.g., QuestaSim, Synopsys VCS) ...
19 days ago

Senior FPGA Verification Engineer

  • Data Capital Inc
  • Santa Clara
... : 3+ years of FPGA verification experience Strong SystemVerilog programming skills ... on experience with UVM (Universal Verification Methodology) Familiarity with industry- ... standard verification tools (e.g., QuestaSim, Synopsys VCS) ...
25 days ago

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