Description: Job Title: FPGA Verification Engineer Location: Santa Clara, CA-Onsite ... Areas Must Have Skills FPGA Verification Engineer Skill 1 8 + Years of in FPGA ... in System Verilog and UVM verification methodology. Experience with industry-standard ...
3 days ago
... Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification ... with UVM (Universal Verification Methodology)Familiarity with industry ... -standard verification tools (e.g., QuestaSim, ...
6 days ago