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Jobs and careers full-time for senior hil validation engineer in Santa Clara (13 jobs)

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  • Skywaves MP LLC
  • Santa Clara
... Description: Role summary Seeking a Senior Design Verification Engineer with 8+ years of experience in ... SystemVerilog and UVM. The engineer will own verification of complex ... closely with RTL, architecture, and validation teams to deliver highquality silicon ...
6 days ago
... on W2 Job Title: Senior Cloud Software Engineer (Threat Prevention & AppID) Location ...
6 days ago
... on W2 Job Title: Senior Cloud Software Engineer (Threat Prevention & AppID) Location ...
6 days ago
... for the enterprise. The Hardware Engineer team works closely to define ... servers and systems. As a Hardware Validation Engineer, you will gain expertise using ...
3 days ago
... , test, yield enhancement and spec validation. Partner with other engineering groups ... including ASIC, ATE, DFT, silicon validation, fab process, software and quality ...
a day ago
  • Apolis
  • Santa Clara
Description: Engineering Technician, Senior Santa Clara , CA 100% onsite 6 ... issues * Works with Custom CPU engineers across a wide range of areas ...
5 days ago
  • ServiceNow, Inc.
  • Santa Clara
... , California in 2004 when a visionary engineer, Fred Luddy, saw the potential ...
3 days ago
  • ServiceNow, Inc.
  • Santa Clara
... , California in 2004 when a visionary engineer, Fred Luddy, saw the potential ...
5 days ago
  • ServiceNow, Inc.
  • Santa Clara
... , California in 2004 when a visionary engineer, Fred Luddy, saw the potential ...
5 days ago
... , California in 2004 when a visionary engineer, Fred Luddy, saw the potential ...
5 days ago
  • Data Capital Inc
  • Santa Clara
Description: Mandate Skills: FPGA Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification experienceStrong SystemVerilog programming skillsHands-on experience with UVM (Universal Verification ...
7 hours ago
  • Data Capital Inc
  • Santa Clara
Description: Mandate Skills: FPGA Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification experienceStrong SystemVerilog programming skillsHands-on experience with UVM (Universal Verification ...
a day ago
  • PaloAlto Networks
  • Santa Clara
Description: Company Description Our Mission At Palo Alto Networks everything starts and ends with our mission: Being the cybersecurity partner of choice, protecting our digital way of life. Our vision is a world where each day is safer and more secure ...
4 days ago