Description: ASIC Design Engineer Location: Santa Clara, CA Onsite ... of the Role As an ASIC Design Engineer , you will play a crucial ... optimization of our cutting-edge ASIC solutions. Your work will directly ...
3 days ago
... Frontend Synthesis/STA Engineer Job Summary We are seeking ... design, synthesis, and static timing analysis. Key Responsibilities 1. ... designs. 3. Conduct static timing analysis (STA) to ensure ... design meets timing requirements. 4. Collaborate with ...
a day ago
... seeking an innovative CAD Software Engineer with particular interest in strategies ... for large scale RTL quality, timing, and power optimization. Such optimization ...
6 days ago
Description: Role Title: Design Verification Engineer Location: Santa Clara, CA, 95054 ( ... verification of a block(s) of complex ASICs and/or IP cores for ...
4 days ago