... : Role summary Seeking a Senior Design Verification Engineer with 8+ years of experience in ... SystemVerilog and UVM. The engineer will own verification of complex digital IPs ... highquality silicon. Key responsibilities - Own verification of one or more IPs ...
5 days ago
Description: Role: FPGA Verification Engineer Location: Santa Clara, CA - Onsite ... a highly motivated and skilled FPGA Verification Engineer to join our dynamic team ... will be responsible for the verification of complex FPGA designs, ensuring ...
5 days ago
... Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification ... with UVM (Universal Verification Methodology) Familiarity with ... industry-standard verification tools (e.g., QuestaSim, ...
3 days ago
... Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification ... with UVM (Universal Verification Methodology)Familiarity with industry ... -standard verification tools (e.g., QuestaSim, ...
6 days ago
... with other engineering groups including ASIC, ATE, DFT, silicon validation, fab ...
18 hours ago
... Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification ... with UVM (Universal Verification Methodology)Familiarity with industry ... -standard verification tools (e.g., QuestaSim, ...
13 hours ago