... Description: Role summary Seeking a Senior Design Verification Engineer with 8+ years of experience in ... SystemVerilog and UVM. The engineer will own verification of complex digital IPs ... silicon. Key responsibilities - Own verification of one or more IPs ...
2 days ago
Description: Role: FPGA Verification Engineer Location: Santa Clara, CA - Onsite ... a highly motivated and skilled FPGA Verification Engineer to join our dynamic team ... be responsible for the verification of complex FPGA designs, ensuring their functionality ...
2 days ago
Description: Role: GenDesign / Inverse Design Ai Engineer Location: Santa Clara, CA Must ... are seeking a Generative AI (GenAI) Design Engineer to join our team and ...
4 days ago
... Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification ... with UVM (Universal Verification Methodology) Familiarity with ... industry-standard verification tools (e.g., QuestaSim, ...
21 hours ago
... Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification ... with UVM (Universal Verification Methodology)Familiarity with industry ... -standard verification tools (e.g., QuestaSim, ...
3 days ago
Description: Title: Software Engineer - Hybrid Mandatory skills: Java, Ruby, ... architecture,ASIC standard verification tools, languages, flows Description: Responsibilities: Design, build, test ...
4 days ago
... Title: Materials Science AI Engineer Job Location: Santa Clara, ... Range: $60hr - $65hrResponsibilities: Design, develop and deploy multi-modal ... solve material physics and design problems.Aggregate, process, ... modeling and analysis.Design, develop and maintain ...
2 days ago
... looking for a AI Engineer for our client in Santa ... CA Job Title: AI Engineer Job Location: Santa Clara ... - $65hrThe Generative AI Design Engineer will design, develop, and optimize generative ... as content creation, product design, intelligent automation, and ...
4 days ago
... Job Title: Senior Cloud Software Engineer (Threat Prevention & AppID) Location: ... : 6+ Months Participate in the design and implementation of threat prevention ... product development cycle, from definition, design, through implementation and test Provide ...
2 days ago
... Job Title: Senior Cloud Software Engineer (Threat Prevention & AppID) Location: ... : 6+ Months Participate in the design and implementation of threat prevention ... product development cycle, from definition, design, through implementation and test Provide ...
2 days ago
Description: Hi Position: AI Engineer Location: Santa Clara, CA - 5D ... Good To have Skills Skill 1 Design, develop and deploy multi-modal ...
2 days ago
... Job Title: Senior Cloud Software Engineer (Threat Prevention & AppID) Location: ... seeking innovators - engineers who seek to design new products, designing ... not exist today. These engineers love to code with a ... looking for talent engineers who take ownership of
4 days ago
... Title: Battery Materials Characterization Technician/Engineer Location : Santa Clara, CA Duration ... anode materials and battery cells Design and develop advanced silicon anode ...
4 days ago
... , California in 2004 when a visionary engineer, Fred Luddy, saw the potential ...
5 days ago