... Description: Role summary Seeking a Senior Design Verification Engineer with 8+ years of experience ... in IP and subsystemlevel verification using SystemVerilog and UVM. The ... silicon. Key responsibilities - Own verification of one or more IPs ...
2 days ago
... Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification ... with UVM (Universal Verification Methodology) Familiarity with ... industry-standard verification tools (e.g., QuestaSim, ...
20 hours ago
... Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification ... with UVM (Universal Verification Methodology)Familiarity with industry ... -standard verification tools (e.g., QuestaSim, ...
3 days ago
Description: Role: FPGA Verification Engineer Location: Santa Clara, CA - ... a highly motivated and skilled FPGA Verification Engineer to join our dynamic ... be responsible for the verification of complex FPGA designs, ensuring their functionality ...
2 days ago
Description: Company Description It all started in sunny San Diego, California in 2004 when a visionary engineer, Fred Luddy, saw the potential to transform how we work. Fast forward to today - ServiceNow stands as a global market leader, bringing ...
5 days ago
... architecture,ASIC standard verification tools, languages, flows Description: Responsibilities: Design, build, test ...
4 days ago