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Jobs and careers for functional safety engineer in Santa Clara (2 jobs)

Lead fpga verification engineer with uvm /verilog system-active requirement
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Lead FPGA Verification Engineer with UVM /Verilog System-Active Requirement

  • Data Capital Inc
  • Santa Clara
... VCS) Experience with code and functional coverage analysis Proficient in debugging ...
17 hours ago

Lead FPGA Verification Engineer with UVM /Verilog System-Active Requirement

  • Data Capital Inc
  • Santa Clara
... VCS)Experience with code and functional coverage analysisProficient in debugging and ...
3 days ago

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