Description: Role: GenDesign / Inverse Design Ai Engineer Location: Santa Clara, CA We ... are seeking a Generative AI (GenAI) Design Engineer to join our team and ... such as content creation, product design, and intelligent automation.Develop forward ...
18 hours ago
Description: Materials Science Ai Engineer at Santa Clara, CA We ... are seeking an AI Scientist/Engineer to join our team in ... and supporting materials discovery and design. The ideal candidate will have ... and automated workflows. Key Responsibilities Design, de
18 hours ago
Description: Role summary Seeking a Senior Design Verification Engineer with 8+ years of experience in ... using SystemVerilog and UVM. The engineer will own verification of complex ...
5 days ago
... Title: Materials Science AI Engineer Job Location: Santa Clara, ... Range: $60hr - $65hrResponsibilities: Design, develop and deploy multi-modal ... solve material physics and design problems.Aggregate, process, ... modeling and analysis.Design, develop and maintain ...
5 days ago
... Job Title: Senior Cloud Software Engineer (Threat Prevention & AppID) Location: ... : 6+ Months Participate in the design and implementation of threat prevention ... product development cycle, from definition, design, through implementation and test Provide ...
5 days ago
... Job Title: Senior Cloud Software Engineer (Threat Prevention & AppID) Location: ... : 6+ Months Participate in the design and implementation of threat prevention ... product development cycle, from definition, design, through implementation and test Provide ...
5 days ago
Description: Role: Materials Science Ai Engineer Location: Santa Clara, CA We ... are seeking an AI Scientist/Engineer to join our team in ... and supporting materials discovery and design. The ideal candidate will have ...
18 hours ago
Description: Hi Position: AI Engineer Location: Santa Clara, CA - 5D ... Good To have Skills Skill 1 Design, develop and deploy multi-modal ...
5 days ago
... . The Hardware Engineer team works closely to define, design and integrate the ... Oracle's Cloud servers and systems. As a Hardware Validation Engineer, you will gain ... latest leading edge server designs. Our systems are designed in house using the ...
2 days ago
... Description: Role: FPGA Verification Engineer Location: Santa Clara, CA ... +Years of Exp in System Verlilog Job Description: We are ... and skilled FPGA Verification Engineer to join our dynamic ... verification of complex FPGA designs, ensuring their functionality, ...
5 days ago
... -on experience with the queuing system such as RabbitMQ, Kafka, experience ...
16 hours ago
Description: 3-5 Years experience in system level testing of datacenter products ...
22 hours ago
... , California in 2004 when a visionary engineer, Fred Luddy, saw the potential ... -based platform seamlessly connects people, systems, and processes to empower organizations ...
2 days ago
... , California in 2004 when a visionary engineer, Fred Luddy, saw the potential ... -based platform seamlessly connects people, systems, and processes to empower organizations ...
4 days ago
... , California in 2004 when a visionary engineer, Fred Luddy, saw the potential ... -based platform seamlessly connects people, systems, and processes to empower organizations ...
4 days ago
... , California in 2004 when a visionary engineer, Fred Luddy, saw the potential ... -based platform seamlessly connects people, systems, and processes to empower organizations ...
4 days ago
... , California in 2004 when a visionary engineer, Fred Luddy, saw the potential ... -based platform seamlessly connects people, systems, and processes to empower organizations ...
5 days ago
... , California in 2004 when a visionary engineer, Fred Luddy, saw the potential ... -based platform seamlessly connects people, systems, and processes to empower organizations ...
6 days ago
Description: Mandate Skills: FPGA Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification experience Strong SystemVerilog programming skills Hands-on experience with UVM (Universal Verification ...
3 days ago
Description: Mandate Skills: FPGA Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification experienceStrong SystemVerilog programming skillsHands-on experience with UVM (Universal Verification ...
6 days ago
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