... performance validation.Identify and resolve design issues in collaboration with engineering ... teams.Participate in design reviews and contribute to verification ... of FPGA, ASIC, and RTL design.Hands-on experience with SystemVerilog ...
30 days ago
... experienced FPGA Verification Engineer to verify complex FPGA designs. You will develop ... performance validation.Identify and resolve design issues in collaboration with engineering ... teams.Participate in design reviews and contribute to ...
a month ago
Description: Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's "Intelligent Cloud" mission. SCHIE delivers the core ...
30 days ago
... looking for a AI Engineer for our client in Santa ... CA Job Title: AI Engineer Job Location: Santa Clara ... - $65hrThe Generative AI Design Engineer will design, develop, and optimize generative ... as content creation, product design, intelligent automation, and ...
4 days ago
Description: Role: GenDesign / Inverse Design Ai Engineer Location: Santa Clara, CA Must ... are seeking a Generative AI (GenAI) Design Engineer to join our team and ...
4 days ago
... : Job Title FPGA RTL design and Board validation Location: ... a highly skilled Senior FPGA Design Engineer with 7 to 15 years ... of experience in RTL design, IP design and development, and FPGA ... have a strong background in design debugging and a deep familiarity ...
17 days ago
... : Job Title FPGA RTL design and Board validation Location: ... a highly skilled Senior FPGA Design Engineer with 7 to 15 years ... of experience in RTL design, IP design and development, and FPGA ... have a strong background in design debugging and a deep familiarity ...
17 days ago
... : Job Title FPGA RTL design and Board validation Location: ... a highly skilled Senior FPGA Design Engineer with 7 to 15 years ... of experience in RTL design, IP design and development, and FPGA ... have a strong background in design debugging and a deep familiarity ...
18 days ago
... : Job Title FPGA RTL design and Board validation Location: ... a highly skilled Senior FPGA Design Engineer with 7 to 15 years ... of experience in RTL design, IP design and development, and FPGA ... have a strong background in design debugging and a deep familiarity ...
21 days ago
... a highly skilled Senior FPGA Design Engineer with 7 to 15 years ... of experience in RTL design, IP design and development, and ... have a strong background in design debugging and a deep familiarity ... deliverables. Key Responsibilities: Design and develop RTL for
29 days ago
... : Job Title FPGA RTL design and Board validation Location: ... a highly skilled Senior FPGA Design Engineer with 7 to 15 years ... of experience in RTL design, IP design and development, and FPGA ... have a strong background in design debugging and a deep familiarity ...
30 days ago
... are looking for DFT / ATPG Engineer for our client in Santa ... , CA Job Title: DFT / ATPG Engineer Job Location: Santa Clara, CA ... : Pay Range: $82hr - $103hrThe DFT Design Engineer will be part of the ... DFT design team responsible for scan/ATPG ...
24 days ago
Description: Job Title: FPGA Design Verification Engineer/Technical Lead II - VLSI Location: ... understanding of FPGA, ASIC, RTL design principles, and architectures. Proficiency in ... , etc. Knowledge of high-speed I/O design and protocols (PCIe, I2C, SPI ...
17 days ago
... performance validation.Identify and resolve design issues in collaboration with engineering ... teams.Participate in design reviews and contribute to verification ... of FPGA, ASIC, and RTL design.Hands-on experience with SystemVerilog ...
28 days ago
Description: Role summary Seeking a Senior Design Verification Engineer with 8+ years of experience in ... using SystemVerilog and UVM. The engineer will own verification of complex ...
2 days ago
... Job Title: Senior Cloud Software Engineer (Threat Prevention & AppID) Location: ... : 6+ Months Participate in the design and implementation of threat prevention ... product development cycle, from definition, design, through implementation and test Provide ...
2 days ago
... Job Title: Senior Cloud Software Engineer (Threat Prevention & AppID) Location: ... : 6+ Months Participate in the design and implementation of threat prevention ... product development cycle, from definition, design, through implementation and test Provide ...
2 days ago
... Engineer - Project Management Polymer Materials Laboratory The Product Design ... Polymers Team is looking for an experienced polymer characterization engineer ... Engineering group within Product Design department. Responsibilities and activities ...
8 days ago
... performance validation.Identify and resolve design issues in collaboration with engineering ... teams.Participate in design reviews and contribute to verification ... of FPGA, ASIC, and RTL design.Hands-on experience with SystemVerilog ...
30 days ago
Description: Role: Silicon Design Package Designer Location: Santa Clara ... highly specialized in semiconductor packaging design, requiring strong EDA tool ... Technical Expertise:Multi-layer package design experience.Understanding of substrate manufacturing ...
2 days ago