... Description: Role summary Seeking a Senior Design Verification Engineer with 8+ years of experience in ... SystemVerilog and UVM. The engineer will own verification of complex digital IPs ... silicon. Key responsibilities - Own verification of one or more IPs ...
2 days ago
Description: Job Title: FPGA Design Verification Engineer/Technical Lead II - VLSI ... design principles, and architectures. Proficiency in SystemVerilog and UVM verification ... operating systems. Proficiency with verification tools such as QuestaSim, ...
17 days ago
... performance validation.Identify and resolve design issues in collaboration with ... teams.Participate in design reviews and contribute to verification strategy.Stay current ... verification tools and methodologies.Strong knowledge of FPGA, ASIC, and RTL design ...
28 days ago
... following areas along with functional verification-SV Assertions, Formal, Emulation.Experience ...
24 days ago
... Areas Must Have Skills FPGA Verification Engineer Skill 1 8 + Years of in FPGA ... a highly motivated and skilled FPGA Verification Engineer to join our dynamic team ... be responsible for the verification of complex FPGA designs, ensuring their functionality ...
8 days ago
Description: Role: FPGA Verification Engineer (19921-1) Location: Santa Clara, CA - ... a highly motivated and skilled FPGA Verification Engineer to join our dynamic team ...
16 days ago
Description: Role: GenDesign / Inverse Design Ai Engineer Location: Santa Clara, CA Must ... are seeking a Generative AI (GenAI) Design Engineer to join our team and ...
4 days ago
... performance validation.Identify and resolve design issues in collaboration with ... teams.Participate in design reviews and contribute to verification strategy.Stay current ... verification tools and methodologies.Strong knowledge of FPGA, ASIC, and RTL design ...
30 days ago
... Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification ... with UVM (Universal Verification Methodology) Familiarity with ... industry-standard verification tools (e.g., QuestaSim, ...
13 hours ago
... Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification ... with UVM (Universal Verification Methodology)Familiarity with industry ... -standard verification tools (e.g., QuestaSim, ...
3 days ago
... Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification ... with UVM (Universal Verification Methodology) Familiarity with ... industry-standard verification tools (e.g., QuestaSim, ...
7 days ago
... : 3+ years of FPGA verification experience Strong SystemVerilog programming skills ... on experience with UVM (Universal Verification Methodology) Familiarity with industry- ... standard verification tools (e.g., QuestaSim, Synopsys VCS) ...
8 days ago
... : 3+ years of FPGA verification experience Strong SystemVerilog programming skills ... on experience with UVM (Universal Verification Methodology) Familiarity with industry- ... standard verification tools (e.g., QuestaSim, Synopsys VCS) ...
11 days ago
... : 3+ years of FPGA verification experience Strong SystemVerilog programming skills ... on experience with UVM (Universal Verification Methodology) Familiarity with industry- ... standard verification tools (e.g., QuestaSim, Synopsys VCS) ...
14 days ago
... : 3+ years of FPGA verification experience Strong SystemVerilog programming skills ... on experience with UVM (Universal Verification Methodology) Familiarity with industry- ... standard verification tools (e.g., QuestaSim, Synopsys VCS) ...
15 days ago
... UVM 3+ years of FPGA verification experience Strong SystemVerilog programming skills ... experience with UVM (Universal Verification Methodology) Familiarity with industry- ... standard verification tools (e.g., QuestaSim, Synopsys VCS) ...
16 days ago
... : 3+ years of FPGA verification experience Strong SystemVerilog programming skills ... on experience with UVM (Universal Verification Methodology) Familiarity with industry- ... standard verification tools (e.g., QuestaSim, Synopsys VCS) ...
17 days ago
... : 3+ years of FPGA verification experience Strong SystemVerilog programming skills ... on experience with UVM (Universal Verification Methodology) Familiarity with industry- ... standard verification tools (e.g., QuestaSim, Synopsys VCS) ...
23 days ago
... : 3+ years of FPGA verification experience Strong SystemVerilog programming skills ... experience with UVM (Universal Verification Methodology) Familiarity with industry ... -standard verification tools (e.g., QuestaSim, Synopsys ...
28 days ago
... : 3+ years of FPGA verification experience Strong SystemVerilog programming skills ... experience with UVM (Universal Verification Methodology) Familiarity with industry ... -standard verification tools (e.g., QuestaSim, Synopsys ...
29 days ago