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Jobs and careers full-time for systems engineer 2 in Santa Clara (2 jobs)

Senior systemverilog verification engineer with fpga
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Senior SystemVerilog Verification Engineer with FPGA

  • Data Capital Inc
  • Santa Clara
Description: Job Discription: 3+ years of FPGA verification experience Strong SystemVerilog programming skills Hands-on experience with UVM (Universal Verification Methodology) Familiarity with industry-standard verification tools (e.g., QuestaSim, ...
28 days ago

Senior SystemVerilog Verification Engineer with FPGA

  • Data Capital Inc
  • Santa Clara
Description: Job Discription: 3+ years of FPGA verification experience Strong SystemVerilog programming skills Hands-on experience with UVM (Universal Verification Methodology) Familiarity with industry-standard verification tools (e.g., QuestaSim, ...
29 days ago

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