What
Where
0
Home Browse jobs About us Contacts
  1. Home
  2. Santa Clara
  3. Design verification engineer
What
Where

Jobs and careers for design verification engineer in Santa Clara (2 jobs)

Senior fpga verification engineer
Full-day
Company
Period
Employment
Source
Location
Sort by:

Senior FPGA Verification Engineer

  • Data Capital Inc
  • Santa Clara
... : 3+ years of FPGA verification experience Strong SystemVerilog programming skills ... on experience with UVM (Universal Verification Methodology) Familiarity with industry- ... standard verification tools (e.g., QuestaSim, Synopsys VCS) ...
19 days ago

Senior FPGA Verification Engineer

  • Data Capital Inc
  • Santa Clara
... : 3+ years of FPGA verification experience Strong SystemVerilog programming skills ... on experience with UVM (Universal Verification Methodology) Familiarity with industry- ... standard verification tools (e.g., QuestaSim, Synopsys VCS) ...
25 days ago

Get new design verification engineer jobs in Santa Clara by email

By creating a job alert, you agree to our Terms You can change your consent settings at any time by unsubscribing or as detailed in our terms.