... Description: 3+ years of FPGA verification experience Strong SystemVerilog programming ... experience with UVM (Universal Verification Methodology) Familiarity with industry ... -standard verification tools (e.g., QuestaSim, Synopsys VCS ...
22 days ago
... Description: 3+ years of FPGA verification experience Strong SystemVerilog programming ... experience with UVM (Universal Verification Methodology) Familiarity with industry ... -standard verification tools (e.g., QuestaSim, Synopsys VCS ...
28 days ago