... for Senior Silicon Design Engineer for our client in Santa Clara, CA Job Title: Senior Silicon Design Engineer ... engineer will work on high-speed multi-gigabit SerDes PHY designs ... and control logic applications, automated design flows for clock tree synthesis ...
17 days ago
Description: We are looking for Senior RTL Design Engineer for our client in Santa ... Clara, CA Job Title: Senior RTL Design Engineer ... - $75.86hr Responsibilities:Perform RTL design of digital components in Verilog ...
a month ago