Description: Silicon Design Package Engineer Location Santa Clara, CA ( ... specialized in semiconductor packaging design, requiring strong EDA tool ... PLA). Technical Expertise: Multi-layer package design experience. Understanding of substrate manufacturing ...
a day ago
Description: Role: Silicon Design Package Designer Location: Santa Clara, ... highly specialized in semiconductor packaging design, requiring strong EDA tool ... PLA).Technical Expertise:Multi-layer package design experience.Understanding of substrate manufacturing ...
8 days ago
Description: Role: Silicon Design Package Designer Location: Santa Clara, ... highly specialized in semiconductor packaging design, requiring strong EDA tool ... PLA).Technical Expertise:Multi-layer package design experience.Understanding of substrate manufacturing ...
14 days ago
Description: Role: Silicon Design Package Designer Location: Santa Clara, ... specialized in semiconductor packaging design, requiring strong EDA tool ... ). Technical Expertise: o Multi-layer package design experience. o Understanding of substrate manufacturing ...
14 days ago
Description: Role: Silicon Design Package Designer Location: Santa Clara, ... highly specialized in semiconductor packaging design, requiring strong EDA tool ... PLA).Technical Expertise:Multi-layer package design experience.Understanding of substrate manufacturing ...
14 days ago
... highly specialized in semiconductor packaging design, requiring strong EDA tool ... PLA).Technical Expertise:Multi-layer package design experience.Understanding of substrate manufacturing ... Design Rules and Assembly Rules. ...
9 days ago
... specialized in semiconductor packaging design, requiring strong EDA tool ... PLA). Technical Expertise: Multi-layer package design experience. Understanding of substrate manufacturing ... Design Rules and Assembly Rules. ...
14 days ago
... : Role summary Seeking a Senior Design Verification Engineer with 8+ years of experience in ... SystemVerilog and UVM. The engineer will own verification of complex ... validation teams to deliver highquality silicon. Key responsibilities - Own verification ...
8 days ago
... Client Job Title: FPGA Design Verification Engineer Job Title: Technical Lead ... skilled FPGA Verification Engineer to join our ... verification of complex FPGA designs, ensuring their functionality, ... will work closely with design engineers to develop and execute ...
18 hours ago
Description: Role: GenDesign / Inverse Design Ai Engineer Location: Santa Clara, CA We ... are seeking a Generative AI (GenAI) Design Engineer to join our team and ... such as content creation, product design, and intelligent automation.Develop forward ...
3 days ago
Description: Role: GenDesign / Inverse Design Ai Engineer Location: Santa Clara, CA Must ... are seeking a Generative AI (GenAI) Design Engineer to join our team and ...
10 days ago
Description: Title: GenDesign / Inverse Design Ai Engineer Location: Santa Clara, CA-Onsite ... are seeking a Generative AI (GenAI) Design Engineer to join our team and ... such as content creation, product design, and intelligent automation. Develop forward ...
13 days ago
Description: Job Title: FPGA Design Verification Engineer/Technical Lead II - VLSI Location: ... understanding of FPGA, ASIC, RTL design principles, and architectures. Proficiency in ... , etc. Knowledge of high-speed I/O design and protocols (PCIe, I2C, SPI ...
23 days ago
... are seeking a Generative AI (GenAI) Design Engineer to join our team and ... such as content creation, product design, and intelligent automation.Develop forward ...
13 days ago
Description: Urgent Opening:DesignVerificationEngineer Job Title:DesignVerificationEngineer Experience: 10+ years Location: San Jose, CA (or other US locations) Job Type: Full-time/Contract KeyRequirements: - Experience working on Subsystems on a Chip ( ...
29 days ago
Description: Job Description: Minimum Qualifications Track record of 'first-pass success' in ASIC development cycles.Bachelor s degree in computer science, Computer Engineering, relevant technical field, or equivalent practical experience.8 to 10 years of ...
a month ago
Description: Role: Silicon Design Package Designer Location: Santa Clara, ... highly specialized in semiconductor packaging design, requiring strong EDA tool ... PLA).Technical Expertise:Multi-layer package design experience.Understanding of substrate manufacturing ...
14 days ago
Description: Role: Package Designer (Semiconductor , Silicon) Location: Santa Clara, ... specialized in semiconductor packaging design, requiring strong EDA ... Technical Expertise: Multi-layer package design experience. Understanding of substrate manufacturing
14 days ago
... groups including ASIC, ATE, DFT, silicon validation, fab process, software and ... to coordinate efforts and resolve silicon issues. Initiate and dr
3 days ago
... Title: Battery Materials Characterization Technician/Engineer Location : Santa Clara, CA Duration ... on silicon anode materials and battery cells Design and develop advanced silicon anode ...
10 days ago