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System integration test lead
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Jobs and careers for system integration test lead in Santa Clara
(1 jobs)
Design verification engineer - cpu subsystem
Company
Yoh - A Day & Zimmerman Company
(
+1
)
Period
Last month
(
+1
)
Schedule
Full-day
(
+1
)
Employment
Full-time
(
+1
)
Source
dice.com
(
+1
)
Location
Santa Clara
(
+1
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Design Verification Engineer - CPU Subsystem
Yoh - A Day & Zimmerman Company
Santa Clara
...
System
Verilog (SV) & UVM, with a focus on developing verification environments, executing
test
...
25 days ago
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