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Jobs and careers for systems engineer principal io in Santa Clara (2 jobs)

Design verification engineer - cpu subsystem
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Design Verification Engineer - CPU Subsystem

  • Yoh - A Day & Zimmerman Company
  • Santa Clara
... Subsystem Looking for a Design Verification Engineer to play a key role in ... solutions. Requires strong expertise in System Verilog (SV) & UVM, with a focus ...
21 hours ago

Design Verification Engineer - CPU Subsystem

  • Yoh - A Day & Zimmerman Company
  • Santa Clara
... Subsystem Looking for a Design Verification Engineer to play a key role in ... solutions. Requires strong expertise in System Verilog (SV) & UVM, with a focus ...
22 days ago

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