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Jobs and careers for systems manager in Santa Clara (2 jobs)

Design verification engineer - cpu subsystem
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Design Verification Engineer - CPU Subsystem

  • Yoh - A Day & Zimmerman Company
  • Santa Clara
... solutions. Requires strong expertise in System Verilog (SV) & UVM, with a focus ...
7 days ago

Design Verification Engineer - CPU Subsystem

  • Yoh - A Day & Zimmerman Company
  • Santa Clara
... solutions. Requires strong expertise in System Verilog (SV) & UVM, with a focus ...
a month ago

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