Description: Position : Generative AI (GenAI) Design Engineer (Contract) Location : Santa Clara, CA ... are seeking a Generative AI (GenAI) Design Engineer to join our team and ... such as content creation, product design, and intelligent automation. Develop ...
5 days ago
... DL Copy Advanced IC Package Design Engineer (CoWoS / 2.5D Packaging)Marvell Santa ...
a day ago
... PythonProficient in using industry-standard design software, including Cadence Virtuoso, ... Calibre DRC, LVS toolsExperience supporting design teams working with analog and ... digital design flowsExcellent communication skills and ability ...
22 days ago
... Client Job Title: FPGA Design Verification Engineer Job Title: Technical Lead ... skilled FPGA Verification Engineer to join our ... verification of complex FPGA designs, ensuring their functionality, ... will work closely with design engineers to develop and execute ...
5 days ago
Description: Role: GenDesign / Inverse Design Ai Engineer Location: Santa Clara, CA We ... are seeking a Generative AI (GenAI) Design Engineer to join our team and ... such as content creation, product design, and intelligent automation.Develop forward ...
8 days ago
... looking for a AI Engineer for our client in Santa ... CA Job Title: AI Engineer Job Location: Santa Clara ... - $65hrThe Generative AI Design Engineer will design, develop, and optimize generative ... as content creation, product design, intelligent automation, and ...
14 days ago
Description: Title: GenDesign / Inverse Design Ai Engineer Location: Santa Clara, CA-Onsite ... are seeking a Generative AI (GenAI) Design Engineer to join our team and ... such as content creation, product design, and intelligent automation. Develop forward ...
17 days ago
... : Job Title FPGA RTL design and Board validation Location: ... a highly skilled Senior FPGA Design Engineer with 7 to 15 years ... of experience in RTL design, IP design and development, and FPGA ... have a strong background in design debugging and a deep familiarity ...
27 days ago
... : Job Title FPGA RTL design and Board validation Location: ... a highly skilled Senior FPGA Design Engineer with 7 to 15 years ... of experience in RTL design, IP design and development, and FPGA ... have a strong background in design debugging and a deep familiarity ...
28 days ago
... : Job Title FPGA RTL design and Board validation Location: ... a highly skilled Senior FPGA Design Engineer with 7 to 15 years ... of experience in RTL design, IP design and development, and FPGA ... have a strong background in design debugging and a deep familiarity ...
29 days ago
Description: Role: GenDesign / Inverse Design Ai Engineer Location: Santa Clara, CA Must ... are seeking a Generative AI (GenAI) Design Engineer to join our team and ...
15 days ago
... are seeking a Generative AI (GenAI) Design Engineer to join our team and ... such as content creation, product design, and intelligent automation.Develop forward ...
18 days ago
... motivated and skilled FPGA Verification Engineer to join our dynamic team ... the verification of complex FPGA designs, ensuring their functionality, performance, and ... . You will work closely with design engineers to develop and execute verification ...
25 days ago
Description: FPGA Verification Engineer Day1 Onsite (Santa ... and skilled FPGA Verification Engineer to join our dynamic ... verification of complex FPGA designs, ensuring their functionality, ... will work closely with design engineers to develop and execute ...
27 days ago
... +Years of Exp in System Verlilog Job Description: We ... and skilled FPGA Verification Engineer to join our dynamic ... verification of complex FPGA designs, ensuring their functionality, performance ... will work closely with design engineers to develop and execute ...
28 days ago
... engineer Santa Clara - California Contract Job description Ability to lead the design ... via APIs and secure workflowsEnsure system designs meet enterprise requirements for security ...
29 days ago
... immediately hiring for a Board Level Test engineer Position type: Contract Location: Santa ... AM PST As a Board Level Test engineer, you will be responsible for ... for PCs and server platforms. Design and implement diagnostic tools and ...
18 days ago
Description: Title:- Board Level Test Engineer Location:- Santa Clara, CA Key ... and troubleshooting for server platforms. Design and implement diagnostic tools and ... troubleshooting methodologies. Develop and maintain test automation using Shell and Python ...
19 days ago
... candidate will design, develop, and maintain automated test frameworks and test suites to ... Selenium and JavaCreate robust automated test scripts for UI, API, and ...
18 days ago
... experienced and proactive Network Hardware Test Engineer to join our growing, remote ... .). You will lead a team of test engineers and work cross-functionally with ...
a month ago