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Jobs and careers for board level reliability engineer from the company Cloudious in Sunnyvale (2 jobs)

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Description: ASIC Engineer (Design Verification) Bay Area, CA ... enable IP/sub-system/SoC level verification. Develop functional tests based ...
7 days ago
... : Title: Infra Silicon Physical Design Engineer Location: Bay Area, CA/Austin ... - Hands-on experience with block level physical design (Floor planning to ... GDSII) - Experience with SoC level integration (multiple blocks, SoC floorplan ...
7 days ago