Description: ASIC Engineer (Design Verification) Bay Area ... verification plans, build verification test benches to enable IP ... . Develop functional tests based on verification test plan. Drive ... defined verification metrics on test plan, functional and code ...
7 days ago
... : Title: Infra Silicon Physical Design Engineer Location: Bay Area, CA/Austin ... closure on 5nm FinFET TSMC process or similar/lower technology nodes ...
7 days ago