Description:
Job Description Work with a dedicated team of engineers, using the latest verification practices, to verify the digital design intent of our SOC's at the block and system level. Engage early in the verification process to understand the verification requirements and participate in UVM or SystemVerilog testbench development. Responsible for creating tests to verify the SOC design at the system or block level and to implement checking mechanisms to ensure coverage closure.Job Requirements 15+ year
Apr 2, 2024;
from:
dice.com