Description:
Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff Drive the effort to maintain RTL quality metrics in complex, hierarchical designs and automating that process for improved efficiency. Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks Work with CAD on the development of pre-production synthesis (Design Compiler) and STA (Primetime) flows Requires a mi
Apr 5, 2024;
from:
dice.com