Description:
Title:Silicon Verification Engineer 5Location: Mountain View,CA(Hybrid)Contract:4+ Month Job Description: Skill set: SystemVerilog and C/C++ coding a must Chip/full system level ASIC Verification skills, and debug skills a must o Debug using waveforms a must, Verdi source level debug a plus System level knowledge a must o System is defined as a test bench containing {CPU + multi-media engines } with hardware based coherency, o System could be a simulation test bench, emulation test bench or a bo
Apr 10, 2024;
from:
dice.com