Design Verification Engineer with UVM,OVM, SystemVerilog & Python

Description:

Role: Design Verification Engineer Location: Santa Clara, CA Interview: Phone/Skype Job Type: Contract Background check: Mandatory Meet and great: Mandatory UVM/OVM/SystemVerilog/Python/C/C++ Responsibilities: Architect and Create verification environments using System-Verilog and Universal verification methodology-UVM IPs and SoCs with embedded CPUs and analog mixed-signal interfaces. Develop test plans and coverage metrics from specifications and writing block and chip-level tests. Creat