Description:
Role: Design Verification Engineer Location: Bay Area, CA Hybrid Job Description: Key Responsibilities: * Develop and implement verification plans for complex SoC designs, with a focus on HighSpeed protocols. * Create and maintain advanced testbenches using SystemVerilog and UVM (Universal Verification Methodology). * Write and execute test cases to verify functional and performance requirements in Highspeed protocols. * Debug and resolve functional and performance issues in collaboration with d
Feb 24, 2025;
from:
dice.com