Description:
Role: Design verification EngineerLocation: Sunnyvale or Austin, USADesign Verification Engineering ServicesTestbench development System Verilog Universal Methodology ( UVM ), Python, and C testsIntegration/development of C tests/Application Programming Interface ( APIs ) and software build flowIntegration of UVM testbenchesTest development and debug, including without limitation tests for functionality, power, performance, error, and connectivity, both for RTL and Gate Level Netlist Design Unde
Feb 24, 2025;
from:
dice.com