Description:
10+ years of senior Pre-silicon verification engineer with PCIE physical, link layer experience in typical networking application products. Require experience with development of UVM and System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS or Cadence Xcelium. Require strong understanding of state of the art of verification techniques, including assertion and metric-driven verification. Require familiarity with verification management tools. Prior yea
Mar 19, 2025;
from:
dice.com