Description:
Senior Design Verification Engineer SV/UVM Contract Long Term Multiple roles- San francisco BayArea Key ResponsibilitiesOwn the verification of complex IP/subsystems using SystemVerilog and UVM methodologyDevelop robust testbenches and testplans from functional specs and architecture docsBuild and maintain scalable UVM environments for IP, subsystem, and SoC-level simulationsWrite directed and constrained-random testcases, ensuring thorough functional and code coveragePerform detailed debugging
Apr 4, 2025;
from:
dice.com