Description:
Title: Infra Silicon Physical Design Engineer Location: Bay Area, CA/Austin, TX Duration: 12 Months Qualification/Experience/Skills Required: - Hands-on tape-out experience performing timing and physical verification closure on 5nm FinFET TSMC process or similar/lower technology nodes - Hands-on experience with block level physical design (Floor planning to GDSII) - Experience with SoC level integration (multiple blocks, SoC floorplan, clocking, and timing analysis) preferred - Expertise in
Apr 8, 2025;
from:
dice.com