Onsite Mid-level Verification Engineer, UVM, SystemVerilog

Description:

Mid-level Verification Engineer with 5-8 years of experience of pure verification in FPGA. This is a pure Verification Engineer role. This position is onsite in the greater San Jose Bay Area. What you will be doing: Purely verification of FPGAProgramming using SystemVerilogDevelop OO testbench infrastructureDevelop test cases using UVMScripting What you will need: 5-8 years in pure VerificationSolid in SystemVerilog programmingExperience with UVM, Universal Verification MethodologyExperience