Description:
At-least 2+ years of experience in emulation (Cadence Palldium, Synopys HAPS) At-least 2+ year of experience in SV/UVM. Experience in complete verification cycle which includes development of test plan, BFM/Driver/Monitor/Scoreboard component development and integration in test bench, stress/corner testing, failure debug, gate level simulations, assertions, and coverage closure. Proficient in SVTB/UVM, C++ testbench along with emulation
Apr 11, 2025;
from:
dice.com