Description:
Job Title: Senior Design Verification Engineer Location: Mountainview, CA What candidate will Be Doing: Strong expertise along-with complex SoC/IP debug is must At-least 5+ years of experience in System Verilog HVL and C/C++. AMBA AXI bus along-with ARM or C based processor Bi-frost/Processor based C and SV/UVM mix Verification. What we are looking for: A bachelor's degree in electrical or computer engineering, accompanied by a minimum of 8 years of experience in ASIC or a related field, or a
Apr 15, 2025;
from:
dice.com