Description:
Mandatory Experience: 7 + years experience in architecting and implementing Design Verification infrastructure and executing the complete verification cycleExperience in the development of UVM based verification environments from scratchExperience with Design verification of Data-center applications like Video, AI/ML, and Networking designsMinimum Qualifications B.S or M.S degree in Electrical Engineering, Computer Engineering or Computer ScienceHands-on experience in Verilog, System Verilog, C/
Apr 15, 2025;
from:
dice.com