Chip-Level Timing Constraint Development Engineer

Description:

Role: Chip-Level Timing Constraint Development Engineer Location: San Jose, CA Onsite Role JD: As a Chip-Level Timing Constraint Development Engineer, you will be responsible for defining, developing, and validating timing constraints for complex ASIC designs at the chip level. Your role will involve close collaboration with cross-functional teams, including RTL designers, physical design engineers, and verification teams, to ensure robust timing closure and sign-off. Key Responsibilities: Deve