Description:
Job Title: Senior ASIC Design Engineer Location:San Jose ,CA Contract: 12+ MonthsWhat candidate will Be Doing: Technical: Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes. Option to also do block level RTL design or block or top-level IP integration. Helping develop efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC changes back to block level. Helping deve
Apr 29, 2025;
from:
dice.com