System Verilog UVM Design Verification Test Engineer

Description:

Job Description: The project relates to the design and verification of a custom controller for analog components. The controller has interfaces such as SPI, Ethernet and AXI to drive the internal components and send data. Responsibilities: UVM/python test development for driving VIPs and other stimulus driversGeneration of test components such as monitors, scoreboards and python modelsCoverage closure and GLS bringup and testing Experience: 6+ years of experience with verification methodologies