Description:
Role: Analog Layout Design Engineer Location: Santa Clara, CA Emp Type: Contract Interview: Phone/Skype JOB DESCRIPTION Minimum 7+ years of experience in Analog and RF layout. Experience developing and leading complex layout IC for high-speed applications in advanced CMOS FinFET technologies such as 7nm and 3nm at the block level and chip level. Experience developing and knowledge of complex layout IC for ultra-low power applications using advanced CMOS FinFET technologies for ASIC/SOC level
May 22, 2025;
from:
dice.com