Description:
8+ yrs exp - FPGA prototyping, FPGA design, emulation and HAPS experiences must. Experience in complete verification cycle which includes development of test plan, BFM/Driver/Monitor/Scoreboard component development and integration in test bench, stress/corner testing, failure debug, gate level simulations, assertions, and coverage closure. Proficient in SVTB/UVM, C++ testbench along with emulation
May 22, 2025;
from:
dice.com