Description:
Position: STA Engineer- Location: San Jose CA (Day-1 Onsite) Interview: video Duration: 12 months Must have/Primary skills: Fullchip timing, SDC changes back to block level, Block/Full chip SDC development, Static Timing Analysis, Primetime/Tempus What You'll Be Doing: Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes. Option to also do block level RTL design or block or top-level IP i
Jun 11, 2025;
from:
dice.com