Description:
Job Title: Design Verification Engineer Location: Sunnyvale, CA / Redmond, WA / Austin, TX Work Type: Full-Time, Onsite (Hybrid No Remote Allowed) Employment Type: Permanent (No Contractors) Experience Range: 7 to 18 Years (No profiles with over 18 years of experience) Key Responsibilities: Develop and maintain UVM/SystemVerilog-based verification environments for IP, subsystem, and SoC level. Understand design specifications and architectural documents to create effective test plans. Write and
Jun 11, 2025;
from:
dice.com