Description:
Role: Design Verification Engineer Location: Mountain View, CA, Sunnyvale CA / Redmond WA / Austin TX Type: Fulltime/Contract (*/W2) Key Responsibilities: Strong understanding of SV and UVM and good debugging skills. Understanding of AMBA protocols. Understand design specs and develop test plans based on functional and architectural requirements Build UVM/System Verilog-based verification environments for IP/subsystem/SoC level testing Develop directed and random testcases, perform coverage an
Jun 26, 2025;
from:
dice.com